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Technical pages
TV interface
Version 0.1 of April 14, 2002
Written by jpb.forth

Timings
Peritel adaptation
Introduction

These specifications describe a 240 lines of 320 pixels TV compatible interface fate to be integrated into the FPGA containing the FORTH core.

Only timings and peritel adaptation are developed in this page. The rest of specifications is described in the VGA interface page.

Timings

The 25 MegaHertz clock of the processor is divided by 4 giving so 6.25 MHz used as pixel time unit. The VGA frame is in refreshed with a 50 Hertz frequency and cut in 312 lines. Frequency lines is so 15.6 KiloHertz.

A simple calculation allows to determine the total clock cycles number by line to 6.25 MHz are 6250000/15600 = 400 (after roundness).

The various timings can be defined in the following way:

The signals of synchronization line and frame are negative (0 during the duration of the pulse). Only one synchronization signal must be created wich is the exclusif or of line and trame signals.

Peritel adaptation

Here is the wiring plan between mini-control board VGA connector and TV peritel connector:

HSYNC signal is in fact exclusive or of VGA interface HSYNC and VSYNC signals.