Entrez dans le monde du FORTH/Enter in world of FORTH

Technical pages
16 and 32 bits FORTH cores

Version 2.0 of April 2, 2006 The particularities of 16 bits core are in color red The particularities of 32 bits core are in color green Written by jpb.forth
Table of registers
Registers description
Table of instructions
Instructions description
Supplementary instructions in F21
Initialization
Interruptions
Code basic instructions FORTH (16 bits core)
Internal peripheral

Introduction

The processor FORTH presented here is based on the F21 instructions feature realized by the company Ultra Technology (5 bits) With a 16 bits data bus and a 21 bits address bus stretchable in 32 (bit A0 is always 0). The data and return stacks are integrated in 16 32 bits format.

Accesses to the memory can be made in 16 bits mode on even addresses only ( unknown bit A0) or in byte mode ( 8 bits) knowing that the bits 0 to 7 of the data bus (respectively 8 to 15) are selected when bit A0 is 1 (respectively in 0). The access mode is defined by the state of a specific control bit (bit B) and is initialized in 16 bits. In case of access to the external memory, only the low 16 bits of the data stack are tranfered. The high 16 bits are set to 0 in read mode, a specific instruction allows to extend the sign to 32 bits.

A zone of 65536 extensions registers maximum gives an indirec access to the internal registers of the processor and to the peripherals integrated to optimize exchanges with these.

Table of registers

All the registers are defined on 16 bits except precision:

Data registers

Extension registers

Adress registers

PC (21 to 32 bits)

Page A (5 to 16 bits) PA

A (16 32 bits)

T (16 32 bits)

S (16 32 bits)

Data stack( 254 elements)
...

Page R (5 to 16 bits) PR

R (16 32 bits)

Return stack ( 255 elements)
...

Stack pointers

Address of T PNTT

Address of R PNTR

Control/State CE

CCCCCCCCCCCCCCCC
C	I	M	B	S	...	EMU	MT

Interruption

Sauvegarde A
SA (16 32 bits)

Sauvegarde Page A SPA

Sauvegarde Page R SPR

Sauvegarde Contrôle/Etat SCE

Integrated interfaces

TIMER

UART_BAUD

UART_CTRL

UART_DATA

Future interfaces ...

Data stack content
(16 32 bits)

...
...

T

S

...
...

Return stack content
(16 32 bits)

...
...

R

...
...

Numbers of extension registers:

Number	Register
0	PA free space
1	PR free space
2	PNTT (512 to 767)
3	PNTR (768 to 1023)
4	CE
5	SA (16 32 bits)
6	SPA free space
7	SPR free space
8	SCE
9 to 255	free space
256	TIMER
257	UART_BAUD
258	UART_CTRL
259	UART_DATA
260 to 511	free space
512 to 767	Data stack (16 32 bits)
768 to 1023	Return stack (16 32 bits)
1024 to 65535	free space

Registers description

The processor is optimized for a of 16 bits data bus and 21 stretchable in 32 bits address bus. The less significant bi of the address bus (bit 0) allows the software to differentiate the even bytes (bit 0 = 0) odd bytes (bit 1 = 1) what implies that this information is always present in the address registers. This bit is ignored by instruction during access to the memory which always remains on 16 bits (the signal A0 does not take ou the processor). Post incrementations is realized on the bit 1 what corresponds to an addition from 2 to the register. Instructions C@ and C! are simulated from the instructions of the processor (to see code basic instructions FORTH).

The program counter or PC does not take into account the bit 0. Instructions are always aligned on the even bytes which constitute the bits 8 to15 of these last ones. The PC is incremented with 2 units in every new line of code (1 unity for the bit 1). The instructions of relative jumps have an always multiple movemen of 2.

The extension registers, all of 16 bits width excepted A and the data and return stacks which are in 32 bits, are placed in a specific memory space of the processor being able to extend until 65536 registers. In that case, bit 0 is taken into account because there is no access possible for these registers under shape of byte. The bits 16 to 31 are the copy of the bit 15 (sign) in the case of the 16 bits registers. If their contents are only of 8 bits (byte of the UART for example), they are placed on the less significant 8 bits of the word (bit 0 to 7) and the most significant 8 24 bits will have the value of the bit 7 for ease the sign bit test.

Here is the representation of the various registers description toward the data and address buses:

Data bus

D15

D14

D13

D12

D11

D10

Data registers (T, and return stack)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

Control/State register

EMU

C corresponds to the Carry
I corresponds to the interruption state (1 for current interruption)
M corresponds to the interruption mask (1 for masked interruption)
B corresponds to the access mode (1 for byte and 0 for 16 bits word)
S corresponds to random access/read only memory mapping (1 for random access memory at 0x00000000)
MT indicates if code 19 is mulu when its value is 1 or addc when its value is 0
EMU indicates that the core is in emulation under UNIX when its value is 1
Address registers (A, R and return stack)

A31

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

Bit A0 to A15 of the return stack is also A16 to A31 for the most significant bits of the PC in call and return of subroutines
(Use of the stack on 2 levels by instructions call, calla and ret)
The state of the bit A0 is unknown when the processor is in 16 bits access mode (B = 0)
Address pages (PA and PR)

A31

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A21 to A31 are present in the 32 bits extension
Program counter PC

A31

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A0 is always 0
A21 to A31 are present in the 32 bits extension

Table of instructions

Code	Name	Description	FORTH	Carry
00000	jmp	Unconditional relative branch	ELSE	Unchanged
00001	jz	Relative branch if T is equal to 0	DUP IF	Unchanged
00010	call	PC pushed in R (2 levels) and relative branch	:	Unchanged
00011	jnc	Relative granch if carry is equal to 0	CARRY? IF	Unchanged
00100	fcw	Extension register reading pointed by R (low 16 bits word) in T, the pointer is then poped	Indefinite	Unchanged
00101	stcw	Extension register writing pointed by R (low 16 bits word) in T, the pointer is then poped	Indefinite	Unchanged
00110	ret	PC poped from R (2 levels)	;	Unchanged
00111	iret	PC poped from R (2 levels) and recovery of registers saved by the interruption	Indefinite	Got back
01000	ftchrp	IF B = 1 THEN reading of the byte pointed by [Page R, R] [R] and incrementation by 1 of [Page R, R] [R] ELSE reading of the 16 bits word pointed by [Page R, R] [R] and incrementation by 2 of [Page R, R] [R] Bits 16 to 31 of T are set to 0	BIT@ IF R@ C@ R> 1+ >R ELSE R@ @ R> 2+ >R THEN	Unchanged
01001	ftchap	IF B = 1 THEN reading of the byte pointed by [Page A, A] [A] and incrementation by 1 of [Page A, A] [A] ELSE reading of the 16 bits word pointed by [Page A, A] [A] and incrementation by 2 of [Page A, A] [A] Bits 16 to 31 of T are set to 0	BIT@ IF A @ C@ 1 A +! ELSE A @ @ 2 A +! THEN	Unchanged
01010	lit	Reading of the word pointed by PC and incrementation by 2 of the PC. Only the low 16 bits word of T is loaded, the high 16 bits word is set to 0	LITERAL	Set to zero
01011	ftcha	IF B = 1 THEN reading of the byte pointed by [Page A, A] [A] ELSE reading of the 16 bits word pointed by [Page A, A] [A] Bits 16 to 31 of T are set to 0	BIT@ IF A @ C@ ELSE A @ @ THEN	Unchanged
01100	strp	IF B = 1 THEN writing of the byte at address pointed by [Page R, R] [R] and incrementation by 1 of [Page R, R] [R] ELSE writing of the 16 bits word at address pointed by [Page R, R] [R] and incrementation by 2 of [Page R, R] [R] Bits 16 to 31 of T are set to 0	BIT@ IF R@ C! R> 1+ >R ELSE R@ ! R> 2+ >R THEN	Unchanged
01101	stap	IF B = 1 THEN writing of the byte at address pointed by [Page A, A] [A] and incrementation by 1 of [Page A, A] [A] ELSE writing of the 16 bits word at address pointed by [Page A, A] [A] and incrementation by 2 of [Page A, A] [A] Bits 16 to 31 of T are set to 0	BIT@ IF A @ C! 1 A +! ELSE A @ ! 2 A +! THEN	Unchanged
01110	swi swab	Software interruption Swapping of the high 16 bits word and the low 16 bits word of T	Indefinite SWAB	Unchanged
01111	sta	IF B = 1 THEN writing of the byte at address pointed by [A page, A] ELSE writing of the 16 bits word at address pointed by [A page, A]	BIT@ IF A @ C! ELSE A @ ! THEN	Unchanged
10000	com	Complement in 1 of T	-1 XOR	Unchanged
10001	rolc	Rotation to the left of T with C	CARRY? IF 2* 1 OR ELSE 2* THEN	Bit 15 31 of T
10010	rorc	Rotation to the right of T with C	CARRY? IF 2/ 32768 2147483648 OR ELSE 2/ 32767 2147483647 AND THEN	Bit 0 of T
10011 MT=0	addc	Addition of S in T if the bi 0 of T is 1	DUP 1 AND IF OVER + THEN	Calculated
10011 MT=1	mulu	Unsigned multiplication of T by R (16x16 32x32 bits) in R;T (32 64 bits with most significant bits in R)	R> U* >R	Unchanged
10100	xorr	Exclusive or of S and T in T	XOR	Unchanged
10101	andd	Logical and of S and T in T	AND	Unchanged
10110	... sxt	Reserve for future application Extension of the sign bit (15) to thebits 16 to 31	... DUP 32768 AND IF -32768 OR ELSE 32767 AND THEN	... Unchanged
10111	addd	Addition of S and T in T	+	Calculated
11000	pop	R poped in T	R>	Unchanged
11001	popa	A copied in T	A @	Unchanged
11010	dup	T pushed in T	DUP	Unchanged
11011	over	S pushed in T	OVER	Unchanged
11100	push	T pushed in R	>R	Unchanged
11101	pusha	T copied in A	A !	Unchanged
11110	nop	One cycle delay	NOP	Unchanged
11111	drop	T dropped	DROP	Unchanged
-	calla	PC pushed in R (2 levels) and jump at an 32 bits address in absolute addressing mode	:	Unchanged

BIT@ rcorresponds to a pseudo FORTH instruction which makes the reading of the bit B state in the CE extension register
A corresponds to a pseudo FORTH variable intended to contain an address

Instructions description

Instructions are defined in a line of code constituted by 16 bits word. There are 3 types of lines of code:

Line with 1 to 3 instructions:

Bit 15

Bit 0

Instruction 1 (5 bits)

Instruction 2 (5 bits)

Instruction 3 (5 bits)

In the case of instructions ret, iret and swi, if they are in instruction 1 (respectively instruction 2) instructions 2 and 3 (respectively 3) will be unknown.

The argument of the instruction lit is placed in the following word.

Line with 1 instruction of relative branch (jmp, jz, call and jnc):

Bit 15

Bit 0

Instruction (5 bits)

Signed movement (10 bits)

The most significant bit of the movement or sign bit ( 10 ) is extended to bits 15 to 11 and to the page before being added to PC register (only when condition is realized for instructions jz and jnc). Movement is multiple of 2 and extends of-2048 in +2046 in bytes (-1024 in +1024 in 16 bits words). A movement of 0 corresponds to the following line of the branch instruction.

Line with 1 instruction for subroutine call in absolute addressing mode:

Bit 15

Bit 0

Less significant bits of address (15 bits)

Most significant bit of address (16 bits)

Only the less significant 5 bits (4 - 0) of the second word are used in 21 bits addressing mode.

Supplementary instructions in F21

iret

This instruction corresponds to the interruption program return. The PC is poped from the return stack (as in the case of the instruction " ret ") and registers A page, A, R page and CE are replaced by their saved values.

fcw

This instruction allows to push the contents of an extension register number of which (or address) is contained in R (low 16 bits word). This number is then removed from the return stack.

stcw

This instruction allows to initialize the contents of an extension register with T and number of which (or address) is contained in R (low 16 bits word). This number is then removed from the return stack.

calla

This instruction allows tocall a subroutine in absolute addressing mode. PC is saved in the return stack on 2 levels and replaced by 2 values contained in the code.

ftchrp, ftchap, ftcha, strp, stap and sta

These instructions possess a supplementary functioning mode. When bit B (for " Byte ") is 0, data are transferred between the external bus and the register T on 16 bits (low word) independently of the state of addresses registers bit 0 . When bit B is 1, data are transferred on 8 bits (bytes) and according to the following method:

In reading, if the bit 0 of address register is 0, bits 15 to 8 of the data bus are transferred in bits 7 to 0 of T. If the bit 0 of address register is 1, bits 7 to 0 of the bus of data are transferred in bits 7 to 0 of T. Bits 15 to 8 of T take the value of the bit 7 to propagate the sign bit of the read byte (-256 in +255). The bits 31 to 16 of T are set to the same value of bit 15 for the 16 bits registers.

In writing, if the bit 0 of address register is 0, bits 7 to 0 of T are transferred in bits 15 to 8 of the data bus. If the bit 0 of address register is 1, bits 7 to 0 of T are transferred in bits 7 to 0 of the data bus.

swi

This instruction allows to activate a software interruption. The PC is pushed in the return stack (as for a " call ") and registers A page, A, R page and CE are copied in their saved equivalents, the mask M is activated (put in 1) and bit B is put in 0 (16 bits access mode).

swab

This instruction allows to swap the high 16 bits word of T with the low 16 bits word.

rolc and rorc

These two instructions replace " shl " and " shr ". They allow to spread more effectively the shift operations on numbers superior to 16 32 bits (32 , 48, ...). " shl " will be simulated by the sequence " dup addd " equivalen for the instruction FORTH " 2 * " and "shr" by " dup rolc drop rorc " equivalent in " 2 / ".

mulu

This instruction replaces addc when MT=1. MT is the bi 0 of extension register CE and read only, it is an indication depending of the core implementation. Mulu instruction executes an unsigned multiplication of T by R and stores the 16 32 most significant bits of the resul in R and the 16 32 less significant bits in T.

sxt

This instruction extends the sign bit (bit 15) of T to the 16 most significant bits.

Initialization

When the RESET signal is applied to the processor, it enter in initialization mode which acts on the various registers in the following way:

- PNTT point the data stack base (512),
- PNTR point the return stack base (768),
- PA is set to zero,
- PR is set to zero,
- A is set to 0,
- C is set to zero,
- M is set to 1 to mask interruption,
- B is set to zero for the 16 bits access mode,
- PC is set to in zero,
- S is set to zero to place the ROM in 0x00000000 (RAM in 0xFFF00000),
- MT is depending of the core architecture, 1 for instruction mulu or 0 for instruction addc (code 17),
- EMU is set to 1 if the core is emulated under UNIX.

In the end of the RESET signal activation, the processor starts at address 0x00000000. The programmer arranges then 8 lines of code (vector of interruption placed at address 0x00000010) allowing a small software initialization followed by the jump at the main program address.

An hardware external programming signal (XMODEM) allows to activate (when XMODEM = 0) access to the ROM of 0x00000000 to 0x000001FF (512 bytes or 256 16 bits words) so that the processor starts on a software downloading sequence from the UART with XMODEM protocol. This sequence makes a jump at address 0xFFF00000 in the end of the transfer (software has been so dowloaded at the same address). The processor discovers a reading at address 0xFFFXXXXX and inhibits then access to the ROM to let appear memory FLASH.

The broadcasting station is host system (PC, MAC or the other one) and the receiver is the processor. The speed of the UART is initialized to 9600 Bauds.

Interruptions

Here is the list of interruption vectors:

Vector (address)	Interruption
0x00000000	RESET (initialization)
0x00000010	Peripheral functions
0x00000020	"swi" instruction Reserve
0x00000030	Incorrect operating code
0x00000040	Overflow of data stack
0x00000050	Overflow of return stack

The main interruption of the processor is the one that is activated with RESET signal. This one provokes initialization described in corresponding paragraph.

The processor possesses an interruption input for internal and external peripheral functions.

The interruption statement is realized in the end of the current code line execution. The processor push the PC in the return stack and makes the saving of registers A, PA, PR and CE in 1 only cycle then positions interruption mask M in 1 (the saved registers are respectively SA, SPA, SPR and SCE). Bit B is initialized in 0 during the interruption entry to allow functioning in 16 bits access mode corresponding to the default mode of the processor. The PC register is loaded with the address 0x00000010 which points the interruption program.

If the programmer decides to authorize the other interruptions at this level, he has to save registers first quoted before unmasking interruptions. Once ended program, he should have to remasquer interruptions and get back registers before launching instruction iret.

This allows to reduce at least the processor response time to an interruption.

Instruction " swi " activates a software interruption of which the vector is address 0x00000020. This interruption is executed about is the state of the mask M.

An interruption is automatically activated on detection of an erroneous operating code. The vector of this interruption is 0x00000030.

The data and return stacks have a size limited to 256 16 32 bits words each. Their initialization positions their pointer in 0x0200 (data) and 0x0300 (return). Every insertion provokes a decrementation of the pointer. Every extraction provokes an incrementation of the pointer. An interruption is generated when the less significan 8 bits of pointers pass of 0xFF in 0x00 in case of insertion or of 0x00 in 0x01 in case of estraction. Vectors are 0x00000040 for the data stack and 0x00000050 for the return stack.

Code basic instructions FORTH (16 bits core)

Here is the implementation of basic instructions FORTH with the processor code of the 16 bits core:

( Evaluation des acces aux registres d'extension.
Version 1.00 du 11 Novembre 2001.
Ecrit par jpb.forth .
)

TELECHARGEMENT

RAZ_ASSEMBLEUR

ASSEMBLEUR
; Evaluation des acces aux registres d'extension.
; Version 1.00 du 11 Novembre 2001
; Ecrit par jpb.forth
;
; Declaration des registres d'extension
; =====================================
;
; Registres de pages
;
PA    EQU    0    ; page pour registre A
PR    EQU    1    ; page pour registre R
;
; Pointeurs des piles
;
PNTT    EQU    2    ; pointeur pile des donnees
PNTR    EQU    3    ; pointeur pile de retour
;
; Controle/Etat
;
CE    EQU    4    ; controle/etat
;
; Masques des differents bits du registre CE
;
MSQC    EQU    %1000000000000000    ; retenue
MSQI    EQU    %0100000000000000    ; etat inter.
MSQM    EQU    %0010000000000000    ; masque inter.
MSQB    EQU    %0001000000000000    ; mode octet
MSQS    EQU    %0000100000000000    ; select. memoire
;
; Sauvegardes interruption
;
SA    EQU    5    ; sauvegarde registre A
SPA    EQU    6    ; sauvegarde page A
SPR    EQU    7    ; sauvegarde page R
SCE    EQU    8    ; sauvegarde controle/etat
;
; Interfaces integres
;
TIMER    EQU    256    ; timer
UBAUD    EQU    257    ; vitesse UART
UCTRL    EQU    258    ; controle UART
UDATA    EQU    259    ; donnees UART
;
; Images des piles
;
DSTACK    EQU    512    ; pile des donnees
RSTACK    EQU    768    ; pile de retour
;
    ORG    0
;
RESET    JMP    TEST    ; Initialisation
;
    ORG    16
;
IRQ    IRET        ; Interruption materielle
;
    ORG    32
;
SWI    IRET        ; Interruption logicielle
;
    ORG    48
;
INSTERR    IRET        ; Instruction illegale
;
    ORG    64
;
DSERR    IRET        ; Debordement pile des donnees
;
    ORG    80
;
RSERR    IRET        ; Debordement pile de retour
;
    ORG    128
;
; Instructions de base
; ====================
;
DUP    DUP        ; n --> n,n
    RET
;
DROP    DROP        ; n --> -
    RET
;
SWAP    PUSH        ; n1,n2 --> n2,n1
    PUSHA        ; equivalent a "2 ROLL"
    POP
    POPA
    RET
;
OVER    OVER        ; n1,n2 --> n1,n2,n1
    RET
;
ROT    PUSH        ; n1,n2,n3 --> n2,n3,n1
    PUSH        ; equivalent a "3 ROLL"
    PUSHA
    POP
    POP
    POPA
    RET
;
PDIDUP    JZ    PDIDUP1    ; ?DUP n --> n,n ou 0
    DUP
PDIDUP1    RET
;
SR    PUSHA        ; >R n --> -
    POP
    POP
    POPA
    PUSH
    PUSH
    PUSH
    RET
;
RS    POP        ; R> - --> n
    POP
    POP
    PUSHA
    PUSH
    PUSH
    POPA
    RET
;
RF    POP        ; R@ - --> n
    POP
    POP
    DUP
    PUSHA
    PUSH
    PUSH
    PUSH
    POPA
    RET
;
PICK    LIT    #PNTT    ; n1 --> n2
    PUSH
    FCW
    ADDD
    PUSH
    FCW
    RET
;
POKE    LIT    #PNTT    ; n1,n2 --> -
    PUSH
    FCW
    ADDD
    PUSH
    STCW
    RET
;
ROLL    DUP        ; n --> -
    PUSH
    LIT    #PNTT
    PUSH
    FCW
    ADDD
    PUSHA
    POP
ROLLA    LIT    #-1
    ADDD
    JZ    ROLLB
    POPA
    PUSH
    FCW
    POPA
    DUP
    PUSH
    LIT    #-1
    ADDD
    DUP
    PUSHA
    PUSH
    FCW
    STCW
    POPA
    PUSH
    STCW
    JMP    ROLLA
ROLLB    DROP
    RET
;
DEPTH    LIT    #PNTT    ; n
    PUSH
    FCW
    COM
    LIT    #1
    ADDD
    LIT    #DSTACK+256
    ADDD
    RET
;
; Multiplication non signee 8x8 --> 16 bits
;
M16    PUSH        ; n1,n2 --> n1*n2
    DUP
    ADDD
    DUP
    ADDD
    DUP
    ADDD
    DUP
    ADDD
    DUP
    ADDD
    DUP
    ADDD
    DUP
    ADDD
    DUP
    ADDD
    POP
    LIT    #255
    ANDD
    ADDC
    RORC
    ADDC
    RORC
    ADDC
    RORC
    ADDC
    RORC
    ADDC
    RORC
    ADDC
    RORC
    ADDC
    RORC
    ADDC
    RORC
    PUSH
    DROP
    POP
    RET
;
; Multiplication non signee 16x16 --> 32 bits
;
M32    PUSH        ; n1,n2 --> (n1*n2)l,(n1*n2)h
    DUP
    DUP
    XORR
    POP
    LIT    #-1
    PUSHA        ; A = -1
    LIT    #16    ; n1,0,n2,cnt=16
M321    PUSH
    PUSH
    OVER
    RORC
    DROP
    JNC    M322
    POP
    DUP
    PUSH
    ADDD
M322    RORC
    PUSH
    RORC
    POP
    POP
    POP
    POPA
    ADDD
    JZ    M323
    JMP    M321
M323    DROP        ; (n1*n2)l,(n1*n2)h,n2,0
    DROP
    RET
;
; Division non signee 32/16 --> 16 et 16 bits
; quotient et reste
;
D32    COM        ; nl,nh,d --> r,q
    LIT    #1    ; r = mod(nh_nl,d)
    DUP        ; q = div(nh_nl,d)
    PUSHA        ; A = 1
    ADDD
    LIT    #16    ; nl,nh,-d,cnt=16
D321    PUSH
    PUSH
    PUSH
    DUP
    ADDD
    POP
    ROLC
    DUP
    POP
    DUP
    PUSH
    ADDD        ; nl,nh,nh-d
    JNC    D324
    PUSH        ; si nh >= d
    DROP
    POPA
    ADDD
    POP
    POP
    JMP    D325
D324    DROP        ; si nh < d
    POP
D325    POP
    LIT    #-1    ; nl',nh',-d,cnt,-1
    ADDD
    JZ    D326
    JMP    D321
D326    DROP        ; q,r,-d,0
    DROP
    CALL    SWAP    ; r,q pour compatibilite FORTH
    RET
;
    ORG    512
;
; Vecteurs pour simulation
; le commentaire donne l'etat attendu de la pile des donnees
;
TEST    LIT    #1    ; 1
    CALL    DUP    ; 1,1
    CALL    DROP    ; 1
    CALL    DUP    ; 1,1
    CALL    OVER    ; 1,1,1
    ADDD        ; 1,2
    CALL    DUP    ; 1,2,2
    LIT    #3    ; 1,2,2,3
    CALL    PICK    ; 1,2,2,1
    ADDD        ; 1,2,3
    CALL    SWAP    ; 1,3,2
    CALL    ROT    ; 3,2,1
    CALL    SR    ; 3,2
    CALL    SWAP    ; 2,3
    CALL    RF    ; 2,3,1
    CALL    OVER    ; 2,3,1,3
    CALL    ROLL    ; 3,1,2
    CALL    ROT    ; 1,2,3
    CALL    DUP    ; 1,2,3,3
    CALL    RS    ; 1,2,3,3,1
    ADDD        ; 1,2,3,4
    LIT    #0    ; 1,2,3,4,0
    CALL    PDIDUP    ; 1,2,3,4,0
    ADDD        ; 1,2,3,4
    CALL    PDIDUP    ; 1,2,3,4,4
    LIT    #5    ; 1,2,3,4,4,5
    CALL    PICK    ; 1,2,3,4,4,1
    ADDD        ; 1,2,3,4,5
    CALL    OVER    ; 1,2,3,4,5,4
    CALL    POKE    ; 1,5,3,4
    CALL    DUP    ; 1,5,3,4,4
    CALL    PICK    ; 1,5,3,4,1
    CALL    DUP    ; 1,5,3,4,1,1
    ADDD        ; 1,5,3,4,2
    CALL    OVER    ; 1,5,3,4,2,4
    CALL    POKE    ; 1,2,3,4
    CALL    DEPTH    ; 1,2,3,4,4
    CALL    M16    ; 1,2,3,16
    CALL    M32    ; 1,2,48,0
    LIT    #2    ; 1,2,48,0,2
    CALL    D32    ; 1,2,0,24
    CALL    DUP    ; 1,2,0,24,24
    CALL    M16    ; 1,2,0,576
    CALL    SWAP    ; 1,2,576,0
    LIT    #37    ; 1,2,576,0,37
    CALL    D32    ; 1,2,21,15
    CALL    M16    ; 1,2,315
    CALL    DUP    ; 1,2,315,315
    CALL    M32    ; 1,2,33689,1
    LIT    #5    ; 1,2,33689,1,5
    CALL    D32    ; 1,2,0,19245
    CALL    M16    ; 1,2,0
    ADDD        ; 1,2
    CALLA    M32    ; 2,0
    ADDD        ; 2
    CALLA    DROP    ; -
;
    END

SIMULATION

( FIN
)

Internal peripherals

TIMER

The TIMER role is to generate a regular interruption for the real-time kernel. It is consisted of a single 16 bits register placed in the extension registers zone of the processor ( 0x0100 ). When the value is zero ( value corresponding to the initialization), the TIMER function is inhibited. A writing of 1 in the register allows to generate an interruption all the 1 ms by incrementing read value.

Interruption is erased by the reading of this same register which gives number of tours made with the counter before interruption is served. This value, coded on 4 bits (D3.. D0), is automatically put back to 0 after reading. The master significant 12 28 bits are always read to 0.

UART

UART allows the transfer of data between the processor and a host computer. This interface is consisted of 3 extension registers of:

UART_BAUD ( 0x0101 ) allowing to choose the transmission frequency multiplied by 16 from the processor frequency divided by 13.5 (1,852 MHz). When the value is 12 ( value corresponding to the initialization), the transmission speed is 9600 bauds with an error of 0,47 %. Value is coded on 4 bits (D3.. D0) allowing to choose among 16 values from 7200 to 115200 bauds :

Speed (bits/s) = Processor Frequency ( Hz) / [13.5*16*(UART_BAUD+1)]

UART_CTRL ( 0x0102 ) who in reading mode gives access to the various state bits of the UART and, in writing mode, serves of interruption mask knowing that each of the state bits can generate one of it (the mask is activated for the initialization):

D15
rxrdy

D14
txrdy

D13
parityerr

D12
framingerr

D11
overrun

D10
reserve

D9
reserve

D8
reserve

D7
reserve

D6
reserve

D5
reserve

D4
reserve

D3
reserve

D2
reserve

D1
reserve

D0
reserve

UART_DATA ( 0x0103 ) who in reading mode gives access to the received byte (rxrdy is put back to zero) and in writing mode allows to send a byte (txrdy is put back to zero). The byte is placed on bits D0 to D7. Bit D8 to D15 D31 is the copy of the bit D7 in reading mode.

Transmission format is fixed to 8 data bits, odd parity and 1 stop bit.