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Technical pages
CAN interface

Version 0.1 of January 22, 2012
Written by jpb.forth
Table of registers
Registers description
Initialization

Introduction

These specifications describe CAN 2.0 interface fate to be integrated into the FPGA containing the FORTH core allowing the interconnection of several boards also other systems using this kind of bus.

This page describes only this interface and its configuration. For all information about the CAN bus, you can use a web searching engine.

Several registers are intended to be accommodated in the extension area of the FORTH core:

a control register,
filter registers for the frames reception,
a transmission frame file,
a reception frame file.

The CAN interface is also an internal peripheral of this processor.

Here is the synoptic plan of the CAN interface:

Table of registers

All the registers are defined on 16 bits:

Numero	Registrer
448 (0x1C0)	CAN_CTRL
449 (0x1C1)	CAN_BRPR
450 (0x1C2)	CAN_BTR
451 (0x1C3)	CAN_TEC
452 (0x1C4)	CAN_REC
453 à 455 (0x3C5...1C7)	Réservé
456 (0x1C8)	CAN_AFMR1_H
457 (0x1C9)	CAN_AFMR1_L
458 (0x1CA)	CAN_AFIR1_H
459 (0x1CB)	CAN_AFIR1_H
460 (0x1CC)	CAN_AFMR2_H
461 (0x1CD)	CAN_AFMR2_L
462 (0x1CE)	CAN_AFIR2_H
463 (0x1CF)	CAN_AFIR2_L
464 (0x1D0)	CAN_AFMR3_H
465 (0x1D1)	CAN_AFMR3_L
466 (0x1D2)	CAN_AFIR3_H
467 (0x1D3)	CAN_AFIR3_L
468 (0x1D4)	CAN_AFMR4_H
469 (0x1D5)	CAN_AFMR4_L
470 (0x1D6)	CAN_AFIR4_H
471 (0x1D7)	CAN_AFIR4_L
472 (0x1D8)	CAN_ID_H
473 (0x1D9)	CAN_ID_L
474 (0x1DA)	CAN_RF
475 (0x1DB)	CAN_DLC
476 (0x1DC)	CAN_DATA_01
477 (0x1DD)	CAN_DATA_23
478 (0x1DE)	CAN_DATA_45
479 (0x1DF)	CAN_DATA_67

Registers description

the CAN_CTRL register allows to control the CAN interface:

D15

D14

D13

D12

D11

D10

RXrdy

TXrdy

reserved

RXmsq

TXmsq

RXclr

TXclr

reserved

AF4

AF3

AF2

AF1

RXrdy read at 1 indicates the presence of at least one frame in the reception file. Write in this bit does not affet it.
TXrdy read at 1 indicates the presence of at least one frame in the transmission file. Write in this bit does not affet it.
RXmsq at 1 hides the reception interrupt activated if RXrdy is at 1.
TXmsq at 1 hides the transmission interrupt activated if TXrdy is at 1.
RXclr erases the reception file when it is set to 1. It is already read at 0.
TXclr erases the transmission file when it is set to 1. It is already read at 0.
LPB loops back TX on RX when it is set to 1. In this case:

the CAN device is not connected to the external bus,
the filters discard the uncompliant frames.

AF1 to 4 allows, when there are set to 1, to take account the corresponding acceptance filters. In initialization, these bits are se to 0, all the frames are accepted.

The CAN_BRPR register contains the generator of time quantum:

D15

D14

D13

D12

D11

D10

BRP15

BRP14

BRP13

BRP12

BRP11

BRP10

BRP9

BRP8

BRP7

BRP6

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

tq = (BRP+1)/25000000

The CAN_BTR register contains the sample configuration of each bit:

D15

D14

D13

D12

D11

D10

réservé

SJW1

SJW0

PRS2

PRS1

PRS0

PHS12

PHS11

PHS10

PHS22

PHS21

PHS20

tbit = (1+PRS+PHS1+PHS2)*tq

The CAN_TEC contains the transmit error counter:

D15

D14

D13

D12

D11

D10

TEC7

TEC6

TEC5

TEC4

TEC3

TEC2

TEC1

TEC0

The CAN_REC contains the receiver error counter:

D15

D14

D13

D12

D11

D10

REC7

REC6

REC5

REC4

REC3

REC2

REC1

REC0

The acceptance filter registers have a 32 bits size distributed in 2 16 bits words:

CAN_AFMR
CAN_AFIR

D15

D14

D13

D12

D11

D10

ID28

ID27

ID26

ID25

ID24

ID23

ID22

ID21

ID20

ID19

ID18

SRR
RTR

IDE

ID17

ID16

ID15

ID14

ID13

ID12

ID11

ID10

ID9

ID8

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

RTR

CAN_AFMRx_H/L contains the mask of the bits to take account by the filter x. A bit is take account when it is set to 1.
CAN_AFIRx_H/L contains the value of the bits to take account by the filter x.
For each configurated filter, the CAN controller compares the frame ID of the received message hide by CAN_AFMRx_H/L with CAN_AFIRx_H/L&CAN_AFMRx_H/L and accepts the frame when equal.
To configurate a filter, first set to 0 the AFx bit, write the wanted values in the registers CAN_AFMRx_H/L e CAN_AFIRx_H/L then set to 1 the AFx bit.
In order to filter the CAN frames, at least 1 of the 4 filters must be configurated.

The frame received or to be transmitted is included in the registers CAN_ID_H/L, CAN_DLC, CAN_DATA_01/23/45/67.
The CAN_ID_H/L register contains:

CAN_ID

D15

D14

D13

D12

D11

D10

ID28

ID27

ID26

ID25

ID24

ID23

ID22

ID21

ID20

ID19

ID18

SRR
RTR

IDE

ID17

ID16

ID15

ID14

ID13

ID12

ID11

ID10

ID9

ID8

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

RTR

The CAN_RF register, only used is reception mode, contains:

D15

D14

D13

D12

D11

D10

AF3

AF2

AF1

AF0

In reading mode only (reception), the AF1 to 4 bits are set to 1 when the received frame is accepted by the corresponding filter.

The CAN_DLC register contains:

D15

D14

D13

D12

D11

D10

DLC3

DLC2

DLC1

DLC0

The CAN_DATA_xx registers contain the frame data:

CAN_DATA

D15

D14

D13

D12

D11

D10

D07

D06

D05

D04

D03

D02

D01

D00

D17

D16

D15

D14

D13

D12

D11

D10

D27

D26

D25

D24

D23

D22

D21

D20

D37

D36

D35

D34

D33

D32

D31

D30

D47

D46

D45

D44

D43

D42

D41

D40

D57

D56

D55

D54

D53

D52

D51

D50

D67

D66

D65

D64

D63

D62

D61

D60

D77

D76

D75

D74

D73

D72

D71

D70

In reading mode, a frame is present if the RXrdy bit is at 1. The software must so read the registers CAN_ID_H to CAN_DATA_67 in this order, whatever the frame length (DLC). Reading of CAN_DATA_67 pops the receive frame in the reception file. The reading must be done again until the RXrdy bit becames 0 signaling that the reception file is empty.

In writing mode, if the TXrdy bit is set to 1, the software can write a new frame to transmit in the registers CAN_ID_H to CAN_DATA_67 in this order, whatever the frame length (DLC). The writing of CAN_DATA_67 pushes the transmit frame in the transmission file. The writing can be done again while the TXrdy bit is set to 1 signaling that the transmission file is not full.

Initialization

During the initialization, as a FORTH core RESET, CAN_CTRL is writen with the value 0x0C00 which hides the interruptions and inhibates the acceptance filters.

The software must so configurate the eventual used filter contents if necessary. CAN_CTRL can so be writen with the corresponding AFx bits, erase the reception and transmission files and eventualy unmask the interruptions if the CAN bus is managed also.